IWJT2012 May 14 - 15, 2012 Shanghai, China

12th International Workshop on Junction Technology
FuXuan Hotel at Fudan University


 

 

Papers collected in IWJT 2004 - 2011 have been indexed by EI database (Compendex)!

General Information
Scope
Call for Paper
Important Dates
Registration
Visa Application
Paper Format
Submission
Keynote/Invited Speakers
Final Program
Best Paper Award
Access
Hotel Reservation
Committees
Contact
Other Information
 
 
Last update:
May. 11, 2012



The 12th International Workshop on Junction Technology (IWJT2012) will be held on May 14 - 15, 2012 in Shanghai, China. The IWJT, started in 2000 and was held annually in Japan or China, is an open forum focused on the needs and interest of the community of a junction formation technology in semiconductors. At the past IWJTs, a number of eminent and experienced scientists and engineers from Asia, America, and Europe presented their latest results on junction technology. The workshop will provide a good opportunity for researchers and engineers to present their new research results, and exchange ideas with leading scientists in this field.

Paper Presentation

The IWJT-2012 will have one plenary and eleven parallel oral sessions. All the accepted papers should be presented by one of the authors at the arranged sessions.
 

Oral Presentation
Presentation time: Keynote speech (45 min): 40 min Talk Time + 5 min Q/A (question/answer)
                           Invited paper (30 min): 25min Talk Time + 5 min Q/A
                           Contributed paper (15 min): 12 min Talk Time + 3 min Q/A
 

A computer and a PC-compatible projector will be provided in each meeting room. Presenters may bring either a CD-ROM, a USB driver, or his/her own laptop to the meeting room. All the presentation files are preferred to be copied into that computer before the session (unless the format of the Powerpoint file does not match well in that computer). Student helpers will assist the presenters before and during the session.
 

Final Program (20120427)

Paper Presentation Schedule

 

May. 14 , 2012

May. 15 , 2012

 

Auditorium, 4th floor
Opening & Plenary Session

Meeting Room 1, 4th floor

Meeting Room 3, 4th floor

8:30

Opening Remark

S1-04

I4-01

8:45

S1-05

 

9:00

K1

S1-06

I4-02

9:15

S1-07

 

9:30

S5-01

I4-03

9:45

K2

S5-02

 

10:00

S5-03

S4-01

10:15

Coffee break

10:30

Coffee break

I6-05

I2-03

10:45

K3

 

 

11:00

S6-02

I2-04

11:15

S6-03

 

11:30

 

 

 

 

11:45

 

 

 

 

 

 

 

 

 

 

Meeting Room 1, 4th floor

Meeting Room 3, 4th floor

Meeting Room 1, 4th floor

Meeting Room 3, 4th floor

13:30

I1-01

I2-01

I7-01

I3-01

13:45

 

 

 

 

14:00

I1-02

I2-02

S6-01

I3-02

14:15

 

 

S7-01

 

14:30

I1-03

S2-01

S7-02

S3-01

14:45

 

S2-02

S7-03

S3-02

15:00

S1-01

S2-03

Coffee break

15:15

S1-02

S2-04

15:30

Coffee break

S7-04

S3-03

15:45

S7-05

S3-04

16:00

I1-04

I6-01

S7-06

S3-05

16:15

 

 

 

S3-06

16:30

I1-05

I6-02

 

S3-07

16:45

 

 

 

 

17:00

I8-01

I6-03

 

 

17:15

 

 

 

 

17:30

S1-03

I6-04

 

 

17:45

 

 

 

 

18:00

 

 

 

 


Presenter list (First name in alphabetical order)

First name

Last name

Affiliation

Country/region

Session No

Paper title

Akira

Uedono

University of Tsukuba

Japan

I6-01

Vacancy-type defects introduced by gas cluster ion implantation to Si probed by monoenergetic positron beams

Bo

Zhang

Shanghai Institute of Microsystem and Information Technology

China

S4-01

Epitaxial growth and properties of NiSiGe

Caroline

Mok

Delft University of Technology

Netherlands

S1-06

Low Pressure Chemical Vapor Deposition of PureB Layers on Silicon for p+n Junction Formation

Chan-lon

Yang

United Microelectronics Corp.

Taiwan,China

I1-01

Improving Device Performance and Variability for 28nm and Beyond Low Power SoC Technology using Advanced Implant Solutions

Christopher

Hinkle

University of Texas at Dallas

USA

I4-03

Reduced NiPtSi Schottky barriers by controlling interface composition and new materials incorporation

Chun Yao

Yang

United Microelectronics Corporation

Taiwan,China

S2-02

Reduction of Thermal Induced Pattern Loading and Device Sensitivity by Various Rapid Thermal Processing Models

Cuiqin

XU

MINATEC Campus

France

S2-01

FDSOI: a solution to suppress boron deactivation in low temperature processed devices

Er-Xuan

Ping

AMAT

USA

I1-02

Two Terminal Diode Steering Element for 3D X-Bar Memory

Fuccio

CRISTIANO

CNRS

France

I6-05

Implantation-induced structural defects in highly activated USJs: Boron precipitation and trapping in pre-amorphised silicon

Genquan

Han

National University of Singapore

Singapore

S1-04

BF2+ Ion Implantation and Dopant Activation in Strained Germanium-Tin (Ge1-xSnx) Epitaxial Layer

Hanbing

He

Xi Dian

china

S5-01

The trapping effect on terahertz AlGaN/GaNresonant tunneling diode

Hiroshi

Itokawa

Semiconductor and Storage Products Company, Toshiba Corporation

Japan

I3-01

Modifications of Growth of Strained Silicon and Dopant Activation in Silicon by Cryogenic Ion Implantation and Recrystallization Annealing

Hongyu

He

PKU-HKUST Shenzhen-Hong Kong Institute

China

S7-02

On the Grain Boundary Barrier Height and Threshold Voltage of Undoped Polycrystalline Silicon Thin-Film Transistors

Injo

Ok

SEMATECH

USA

I1-03

Conformal, Low-damage Shallow Junction Technology (Xj~5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node

Jay

Mody

IBM

USA

I6-03

Scanning Spreading Resistance Microscopy for carrier profiling beyond 32nm node

Jeff

Wu

Taiwan Semiconductor Manufacturing Company Ltd

Taiwan,China

I7-01

Modeling Challenges of Advanced Doping Technologies

Jinjuan

Xiang

Institute of Microelectronics, Chinese Academy of Sciences

China

S3-03

Band alignment of high-k dielectric on SiO2/Si stack

John

Borland

None

USA

S1-02

Comparison of BF2, In, Ga, C+Ga & In+BF2 Dopant for 22nm Node Bulk & PD-SOI HALO Implantation or Ground Plane Back-Gate Doping for FD-SOI CMOS Technologies

Julien

Venturini

Excico

France

I2-01

Laser Thermal Annealing: Enabling ultra-low thermal budget processes for 3D junctions formation and devices

Jun

Chen

Fudan university

China

S5-03

Investigation of Schottky Junction and MOS Technology for III-V Compound Semiconductor MOSFET Application

jun

huang

Nanjing University of Posts and Telecommunications

china

S7-01

Numerical Simulation of Static and Dynamic Operation Performance of SOI VLT LDMOS Considering Electrical-thermal Couple Effects

Kangliang

Wei

Peking University

China

S7-04

Study of Carrier Transport through GexSi1-x/Si Heterojunctions by Using 2D Monte Carlo Simulation Method

Karuppanan

Sekar

Nissin Ion Equipment USA Inc

USA

I1-04

Application of Cluster Ion (carbon) implantation for Strain applications

Keping

Han

Applied Materials

USA

S1-01

A Novel Plasma-based Technique for Conformal 3D FINFET Doping

Kuan-Yu

Chen

National Sun Yat-Sen University

Taiwan,China

S6-01

The Effects of Block Oxide Length (Lbo) and Height (Hbo) in a bMOS

Lerong

Fu

Jianghan university

china

S1-03

Electroluminescence from n-Mn doped ZnO/n-GaN heterojunction light-emitting diodes

Li

Zhang

Toshiba Corporation

Japan

I6-02

Site-Specific and High-Spatial-Resolution Scanning Spreading Resistance Microscopy (SSRM) and Its Applications to Si Devices

Liang

Li

Xidian University

China

S5-02

An efficient model for trap analysis in C-V measurement for AlGaN/GaN heterostructure

Masahiro

Koike

National Institute of Advanced Industrial Science and Technology (AIST)

Japan

S3-01

Schottky Barrier Height Modulation of NiGe/Ge Junction by P and Chalcogen (S, Se, or Te) Co-introduction for Metal Source/Drain Ge nMOSFETs

Meisheng

Zhou

SMIC

China

K3

Win-Win Collaboration to Meet the New Challenges in Advanced Technology Research & Development

Michael

Thompson

Cornell University

USA

I2-04

Deactivation Behavior of Thermodynamically Limited Metastable Dopant Concentrations During Millisecond and Sub-millisecond Thermal Processes

Ming

Liu

IMECAS

China

I1-05

Rectifying-based RRAM crossbar array for high density storage applications

Naoto

Horiguchi

IMEC

Belgium

I3-02

Junction Strategy for 1x nm Technology Node with FINFET and High Mobility Channel

Paul

Timans

Mattson Technology, Inc.,

U.S.A.

I2-02

Flat-Top Flash Annealing (TM) For Advanced CMOS Processing

Peng

Xu

Fudan University

China

S3-05

A novel MOSFET structure with asymmetric Schottky and P-N junction source/drain on bulk silicon substrate

Peter Folmer

Nielsen

Capres A/S

Denmark

I6-04

Microprobe Metrology for direct Sheet Resistance and Mobility characterization

Qing-Tai

Zhao

Forschungszentrum Juelich

Germany

I4-01

Planar and Nanowire Schottky Barrier MOSFETs on SOI with NiSi and Epitaxial NiSi2 Contacts

Reza

Arghavani

Lam Research Corporation

U.S.A.

I8-01

New Generations of Tools Sets That Enable FDSOI and 3-D Tri-Gate Technologies

Sagara

Akihiko

Japan

Japan

S2-04

Detection and Characterization of Residual Damage in Low-Dose Arsenic Implanted Silicon after High-Temperature Annealing

Seiichiro

Higashi

Hiroshima University

Japan

I2-03

Application of Atmospheric Pressure Micro-Thermal-Plasma-Jet to Ultra Rapid Thermal Annealing for Semiconductor Device Fabrication

Shih-Wen

Hsu

National Sun Yat-Sen University

Taiwan,China

S3-02

Simulation Study of Junctionless Vertical MOSFETs for Analog Applications

Shu

Qin

Micron Technology

USA

K1

PLAD (Plasma Doping) on 22nm Technology Node & Beyond - Evolutionary and/or Revolutionary?

Shu

Qin

Micron Technology, Inc.

USA

S1-07

PMOS Device Performance Improvement by using Buried Contact Implants

SHU-HUAN

SYU

National Sun Yat-Sen University

Taiwan,China

S7-05

Junction vs. Junctionless Vertical MOSFET by Using Partial SOI Structure: A 2D Simulation Study

Wanling

Deng

Jinan University

China

S7-03

Explicit Approximation of Surface Potential for Fully-depleted Polysilicon Thin-Film Transistors

Wenjie

Yu

Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences

China

S3-07

Hole mobility enhancement of quantum-well p-MOSFETs on sSi/sSi0.5Ge0.5/sSOI heterostructure

Xiaolei

Wang

Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

PR China

S7-06

Investigation of band structure at metal-gate/high-k interface of metal oxide semiconductor device with high-k and metal gate stack

Yee-Chia

Yeo

National University of Singapore

Singapore

I4-02

Self-aligned Contact Metallization for III-V Channel Field-Effect Transistors

Yohei

Hayase

Semiconductor Company,Toshiba Corporation

Japan

S6-03

Applications of Site-Specific Scanning Spreading Resistance Microscopy (SSRM) to Failure Analysis of Production Lines

Yonggen

He

Semiconductor Manufacturing International Corporation

China

S2-03

Process Match between DSA and LSA for Ultra-shallow Junction Formation

Yonggen

He

Semiconductor Manufacturing International Corporation

China

S3-04

Investigation of groove surface induced by strain relaxation in selective epitaxy SiGe process

Yoshiki

Nakashima

Nissin Ion Equipment Co., Ltd.

Japan

S1-05

Phosphorous Transient Enhanced Diffusion Suppression with Cluster Carbon Co-implantation at Low Temperature

Youhei

Miyata

Tokyo Institute of Technology

Japan

S6-02

Soft X-ray Photoelectron Spectroscopy Study of Boron Doped on Top Surfaces and Sidewalls of Si Fin Structures

You-Ren

Lu

National Sun Yat-Sen University

Taiwan,China

S3-06

Short-Channel Characteristics of Self-Aligned Dual-Channel Source/Drain-Tied MOSFETs

Yuri

Erokhin

Applied Materials

USA

K2

Device Scaling and Performance Improvement: Advances in Ion Implantation and Annealing Technologies as Enabling Drivers

 


 

Workshop Scope
(Papers are solicited in, but not limited to the following)

  • Doping Technology --- Ion implantation, plasma doping, gas and solid doping
  • Annealing Technology --- Rapid thermal process, laser annealing, flash annealing, SPE, lattice damage and defects
  • Junction Technology for Novel CMOS Device Structures --- Junction for SOI, strained Si, SiGe, Ge, Schottky barrier S/D MOSFET, and FinFET(Tri-gate FET)
  • Silicide and Contact Technology for CMOS --- Silicide materials and salicide technology, elevated S/D, low barrier contact, surface pre-treatment
  • Junction and Contact Technologies for Compound Semiconductors and Quantum Devices --- Schottky and ohmic contacts to wide bandgap compound semiconductors, junction and contact technologies for carbon nanotube, graphene and other nano-, quantum devices, hetero-junction devices
  • Characterization for Shallow Junction --- Physical and electrical characterization of ultra-shallow junction
  • Modeling and Simulation --- Modeling and simulation of ultra-shallow junction formation of CMOS
  • Equipment, Materials and Substrates for Junction Technology

 

Paper Submission
Prospective authors are requested to submit a detailed abstract in English (Word Template). After reviewing, notification of acceptance will be sent to the authors and the authors will be required to submit their camera-ready full-length papers for proceedings publication. Camera-ready full-length late news papers are also accepted. The proceedings will have an IEEE catalogue number and will be collected in IEEE publication database ---- IEEE X’plore
Ò. The proceedings will be published before the workshop and distributed at the workshop.

 

Proceedings Media

IEEE Catalog Number

ISBN

USB

CFP12796-USB

978-1-4673-1256-1

Print

CFP12796-PRT

978-1-4673-1255-4

 

Important dates (Deadline extended!)

Deadline for Regular Paper Abstract Submission: Feb. 20, 2012

Notification of Regular Paper Acceptance: Mar. 1, 2012

Deadline for Camera-Ready Full-Length Paper Submission: Apr. 1, 2012

Deadline for Late News Submission: Apr. 1, 2012

On-line submission at web-site http://www.iwjt.org is preferred.

OR email submission with a cover letter to iwjt@fudan.edu.cn can be as an alternative.


Co-Sponsored by

Fudan University
The Japan Society of Applied Physics - Silicon Technology Division

 

Technical Co-Sponsored by
IEEE EDS
IEEE EDS Shanghai Chapter
IEEE EDS Japan Chapter

Supported by
Fudan University
Natural Science Foundation of China
Nissin Ion Equipment Co., Ltd.
 

 

 
 



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